AMD Carrizo APU on the 28nm Node Will Have Stacked DRAM On Package - Alleges Italian Leak

[RUMOR] Notice the shiny tag at the start. Keep. We have received some data regarding AMD'south upcoming APU Carrizo, this information is unverified then I will be treating it equally a rumor. The study comes from the Italian site bitsandchips.information technology and states that AMD's upcoming flagship APUs will take Stacked DRAM while maintaining the 28nm Node.

The Quite One-time 'Leaked' Roadmap

Carrizo APU volition exist based on the 28nm Node and take HBM (High Bandwidth Retentiveness)

Now it goes without saying, that yous need to keep that compression of salt handy throughout this post. However this news, if true, is very interesting. We know for a fact that APUS do good a lot from good memory and if these APUs will truly back up HBM then we can look to run across some very substantial performance per clock gains while jumping from Kaveri to Carrizo fifty-fifty while staying on the same node. Another important point to notation is that with the Carrizo APU the implementation of HSA will exist perfected resulting in probably meaning in compute besides as gaming.

Now we already know that AMD is working with Hynix to create Stacked DRAM.  We likewise know that this retention will come in 2 types, namely 3DS and HBM (Don't be fooled by the lack of 3D in this proper noun, both are stacked). The memory that is in question hither is the HBM variant type which will feature the highest bandwidth and I know for a fact that at that place are 2 types already in production. Namely the ii-Hi and iv-Hello variants. You can notice the detailed analysis of the same in my Pascal Architecture Analysis. Now the max bandwidth of a single HBM is 128-256 GBps (compare this to the 28GBps of GDDR5), so we are looking at an insane growth in bandwidth, albeit at reduced clocks (most probably around 1000Mhz).

Wccftech	GDDR5	two-Hullo HBM 'Stacked DRAM'	4-Hi HBM 'Stacked DRAM'
I/O	32	512	1024
Max Bandwidth Per Pivot	7 Gbps	i Gbps	1 Gbps
Max Bandwidth	28 GBps	64 GBps	128 GBps
Voltage	1.35 - i.65	~1.2	~1.two
Command Input	Single	Dual	Dual
Layers	one	2 + 1	4 + 1

Now nosotros previously received a much more authentic report that the APU would actually feature DDR4 support but this is obviously better. Carrizo APU's die size volition be smaller than Kaveri APU according to the same source, though I am not sure how they aim to accomplish this if the HBM is truly "on-package". The Stacked DRAM will be manufactured on the 20nm node but the APU will stay at 28nm. Previous leaks had suggested that the upcoming APU will be compatible with the FM2+ socket and take TDP no greater than 65W. However the thing is, the last authentic leak was quite a while back and AMD's plans could have changed in the meantime. We will be waiting for more information on this front and in the concurrently this should serve as skillful nutrient for thought, if nothing else.

#AMD Carrizo APU with Stacked DRAM? This should be good. http://t.co/SdMtB4Bne2

— Usman Pirzada (@usmanpirzada) July 12, 2022

Source: https://wccftech.com/amd-carrizo-apu-28nm-stacked-dram-alleges-italian-leak/

Posted by: espinalusety1958.blogspot.com

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